1. Field of the Invention
The present invention pertains to the field of integrated circuit (IC) packaging. More particularly, the present invention relates to a three-dimensional (3D) multi-chip package design that provides a high performance, high-density packaging option within a single chip footprint.
2. Description of Related Art
Electronic circuits integrated in a semiconductor substrate are commonly housed within packages suited to the particular integrated circuit (IC) device. A typical semiconductor package comprises a leadframe which interconnects the IC to external circuitry located on an printed circuit board (PCB). A standard leadframe is larger than the size of the integrated circuit die so that bonding pad regions on the die can be wire-bonded to extensions or “fingers” of the leadframe. After the IC has been wire-bonded to the leadframe, the assembly is normally encapsulated in plastic or some other type of packaging material. Terminals connected to the leadframe fingers extend outside the packaging material to provide points of interconnection to other electronic components.
Most large-scale ICs are presently packaged in plastic or ceramic packages with metal leads extended therefrom for soldering to a PCB or for insertion into a socket. Typically, these IC packages are configured as dual-in-line or quad-flat packages. In most instances, only a single IC chip is contained within a package, although multiple chips are sometimes contained within a package. The circuit density resulting from this packaging technology is not very great since the ceramic or plastic package consumes relatively large areas of the mounting surface, usually a PCB, particularly if a socket is used.
Moreover, PCBs are becoming smaller and denser. A compact packaging technology is needed when mounting area is limited dictating that circuit elements be closely spaced. PCBs have typically been designed so that semiconductor devices in the form of packaged semiconductor die are mounted thereon to make a final circuit. For memory boards, the drive for increased memory capacity is limited by board space. Thus, when the size of the board is fixed, the number of devices that can possibly be mounted on the board is limited. A module consisting of a plurality of semiconductor devices is then used to densely dispose the semiconductor devices.
A continuing goal of the semiconductor industry is to maximize circuit density. One past scheme for increasing circuit density has been to house multiple semiconductor die in a single package. For example, an IC package containing two memory chips can double the density of a memory system without increasing the PCB area containing the memory chips. The problem with prior art multi-chip packages, however, is that they either require the use of a specially adapted custom package, or they impose size restrictions on the semiconductor dies that may be housed together. In addition, conventional dual die semiconductor packages often mandate a custom bonding pad routing for the IC's so that interconnection can be made to a single leadframe. Thus, past efforts of fabricating multi-chip packages have often resulted in costly package designs limited in use to specific die sizes or particular bonding pad configurations.
Several methods exist for fabricating a semiconductor multiple chip module. One such method uses a laminated co-fired ceramic substrate onto which bare semiconductor die are directly attached to the ceramic mounting surface and are wire bonded to conductive areas on the mounting surface, or are inverted and connected directly to metallized areas on the ceramic mounting surface by, for example, a solder-bump technique. This multiple chip module technology has several limitations, however. Interconnecting multiple IC's on a single ceramic mounting surface requires deposition of a metallic material in a pattern which desirably avoids cross-overs. Furthermore, a disadvantage of direct chip attach is the difficulty of burn-in before module assembly. Burn-in is performed to screen out weak devices. If a module fails during burn-in due to a weak device, the entire module must be discarded or repaired after burn-in, whereas if each component of the module could be burned-in prior to module assembly, the yield for functional modules can be increased.
Another method of fabricating a semiconductor multiple chip module involves tape automated bonded (TAB) semiconductor die to a flexible circuit leadframe. The semiconductor die are tested as discrete units before being mounted, or they can be tested in the final circuit form after the TAB process. After testing and reworking, the flexible circuit leadframe is encapsulated. The die and circuitry on the leadframe, except for outer portions of the leadframe, are encapsulated in a mold forming a single package body for the entire module. The disadvantage to this approach is that repair of the module after fabrication would cause the entire module to be rejected.
Another approach to form a multiple chip module is to stack pin grid arrays (PGAs) and/or ball grid arrays (BGAs). A bottom substrate is provided with copper pins in a conventional manner. Semiconductor die are then flip-chip mounted to chip carrier substrates. An interposer physically and electrically couples a chip carrier substrate to another chip carrier or to the bottom substrate by way of solder joining the interconnections. The metal pins of the PGAs and the interposers provide the stand-off between the carriers to keep them from collapsing onto each other.
Standard single package PGA and BGA options have not been capable of supporting multi-chip formats without expanding the footprint of the package. An expansion of the footprint of the package increases the needed length of the wiring traces on the substrates to interconnect the devices. As a result, an ever increasing need exists for other passive devices such as decoupling capacitors. Further, the pre-testing of each device requires the pre-packaging of each device that when assembled increases the trace lengths and interface joints.